649 lines
24 KiB
C++
649 lines
24 KiB
C++
// lr1121_malnus.hpp — LR1121 LoRa driver for this exact board
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//
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// Hardware:
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// /dev/spidev0.0 SCK=GPIO11, MOSI=GPIO10, MISO=GPIO9, NSS=GPIO8
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// GPIO24 BUSY (DIO0)
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// GPIO25 nRESET
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// DIO5 RF-switch RFSW0 — chip-driven (HIGH in RX)
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// DIO6 RF-switch RFSW1 — chip-driven (HIGH in TX/TX_HP)
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//
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// Crystal oscillator module (no TCXO). SetDioAsRfSwitch configures DIO5/DIO6
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// so the chip drives the module's RF switch automatically.
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//
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// Opcodes verified against:
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// LR1121 User Manual Rev 1.2 (UM.LR1121.W.APP, Table 13)
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// Semtech SWDR001 (https://github.com/Lora-net/SWDR001)
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#pragma once
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#include <chrono>
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#include <cstdio>
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#include <cstring>
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#include <thread>
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#include <fcntl.h>
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#include <linux/gpio.h>
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#include <linux/spi/spidev.h>
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#include <sys/ioctl.h>
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#include <unistd.h>
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namespace lr1121 {
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// ── Opcodes ──────────────────────────────────────────────────────────────────
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// System
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constexpr uint16_t OC_GET_VERSION = 0x0101;
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constexpr uint16_t OC_GET_ERRORS = 0x010D;
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constexpr uint16_t OC_CLEAR_ERRORS = 0x010E;
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constexpr uint16_t OC_CALIBRATE = 0x010F; // 1B bitmask
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constexpr uint16_t OC_SET_REGMODE = 0x0110; // 1B: 0=LDO 1=DCDC
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constexpr uint16_t OC_CALIBRATE_IMAGE = 0x0111; // 2B: f1,f2 in 4-MHz steps
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constexpr uint16_t OC_SET_DIO_AS_RFSW = 0x0112; // 8B: enable + 7 mode bytes
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constexpr uint16_t OC_SET_DIOIRQ = 0x0113; // 8B: irq1(4B) + irq2(4B)
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constexpr uint16_t OC_CLEAR_IRQ = 0x0114; // 4B mask
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constexpr uint16_t OC_REBOOT = 0x0118; // 1B: 0=app 1=bootloader
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constexpr uint16_t OC_GET_VBAT = 0x0119; // → 1B raw ADC (VBAT ≈ raw/34.0 V)
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constexpr uint16_t OC_SET_STANDBY = 0x011C; // 1B: 0=RC 1=XOSC
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// Buffer
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constexpr uint16_t OC_WRITE_BUF8 = 0x0109; // N bytes
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constexpr uint16_t OC_READ_BUF8 = 0x010A; // 1B offset + 1B len → data
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constexpr uint16_t OC_CLEAR_RXBUF = 0x010B;
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// Radio
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constexpr uint16_t OC_GET_RXBUF_STA = 0x0203; // → [len, ptr]
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constexpr uint16_t OC_GET_PKT_STATUS = 0x0204; // → [rssi, snr, sig_rssi]
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constexpr uint16_t OC_SET_LORA_NET = 0x0208; // 1B: 0=private 1=public
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constexpr uint16_t OC_SET_RX = 0x0209; // 3B timeout in RTC steps
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constexpr uint16_t OC_SET_TX = 0x020A; // 3B timeout (0 = no timeout)
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constexpr uint16_t OC_SET_RF_FREQ = 0x020B; // 4B Hz big-endian
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constexpr uint16_t OC_SET_PKT_TYPE = 0x020E; // 1B: 0x02=LoRa
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constexpr uint16_t OC_SET_MOD_PARAM = 0x020F; // SF,BW,CR,LDRO
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constexpr uint16_t OC_SET_PKT_PARAM = 0x0210; // preamble(2B),hdr,len,crc,iq
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constexpr uint16_t OC_SET_TX_PARAMS = 0x0211; // pwr(int8),ramp
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constexpr uint16_t OC_SET_PKT_ADRS = 0x0212; // tx_base,rx_base
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constexpr uint16_t OC_SET_FALLBACK_MODE = 0x0213; // 1B: 0x01=STBY_RC
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constexpr uint16_t OC_SET_PA_CFG = 0x0215; // pa_sel,supply,duty,hp_max
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// ── Constants ─────────────────────────────────────────────────────────────────
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// IRQ bits (LR1121 UM Table GetStatus / SetDioIrqParams)
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constexpr uint32_t IRQ_TX_DONE = (1u << 2);
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constexpr uint32_t IRQ_RX_DONE = (1u << 3);
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constexpr uint32_t IRQ_CRC_ERR = (1u << 7);
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constexpr uint32_t IRQ_TIMEOUT = (1u << 10);
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constexpr uint32_t IRQ_ALL = 0x1BF80FFCu; // all defined IRQ bits
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// Calibration bitmask (Calibrate command)
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constexpr uint8_t CALIB_ALL = 0x3F; // LF_RC|HF_RC|PLL|ADC|IMG|PLL_TX
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// Modulation
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// SF: 0x05=SF5 .. 0x0C=SF12
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// BW: 0x01=15.6kHz 0x02=31.2 0x03=62.5 0x04=125 0x05=250 0x06=500
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// CR: 0x01=4/5 0x02=4/6 0x03=4/7 0x04=4/8
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// PA: 0x00=LP (≤15 dBm) 0x01=HP (≤22 dBm)
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constexpr uint32_t FREQ_433 = 433'050'000u;
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constexpr uint32_t FREQ_868 = 868'000'000u;
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constexpr uint32_t FREQ_2400 = 2'403'000'000u;
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// ── Public types ──────────────────────────────────────────────────────────────
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struct Config {
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const char *spi_path = "/dev/spidev0.0";
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uint32_t spi_hz = 8'000'000;
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const char *gpio_chip = "/dev/gpiochip0";
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unsigned busy_gpio = 24; // DIO0 / BUSY
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unsigned reset_gpio = 25; // nRESET
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uint32_t freq_hz = FREQ_433;
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uint8_t sf = 0x07; // SF7
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uint8_t bw = 0x04; // 125 kHz
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uint8_t cr = 0x01; // 4/5
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int8_t tx_dbm = 14; // -17..+22 dBm
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uint8_t pa_sel = 0x01; // 0x00=LP(≤15dBm) 0x01=HP(≤22dBm)
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// pa_supply: 0x00=internal VREG (use for ≤14 dBm), 0x01=VBAT direct (>14 dBm)
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// RadioLib: "Must be set to PA_SUPPLY_VBAT when output power is more than 14 dBm."
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uint8_t pa_supply = 0x00;
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// use_dcdc: false=LDO (safe default for Pi; no DCDC inductor required)
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// true=DCDC (higher efficiency; only if module has external DCDC components)
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bool use_dcdc = false;
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bool lora_wan = false; // false = private sync word
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bool verbose = false;
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};
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struct RxInfo {
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int8_t rssi_dbm = 0;
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int8_t snr_db = 0;
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int8_t signal_rssi_dbm = 0;
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};
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struct ChipVersion {
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uint8_t hw;
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uint8_t type; // 0x03 = LR1121
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uint8_t fw_hi;
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uint8_t fw_lo;
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};
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// ── Radio class ───────────────────────────────────────────────────────────────
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class Radio {
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public:
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bool begin(const Config &cfg);
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void end();
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bool send(const uint8_t *data, uint8_t n); // true = TX_DONE, false = timeout
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// Returns byte count received; -1 = timeout, -2 = CRC error.
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int receive(uint8_t *buf, uint8_t cap, uint32_t timeout_ms,
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RxInfo *rx_info = nullptr);
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ChipVersion getVersion();
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// Open SPI + GPIOs and hard-reset only — no calibration.
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// Use for --reset / diagnostic commands when begin() would hang.
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bool beginRaw(const Config &cfg);
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void reboot(bool stay_in_bootloader = false);
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private:
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Config cfg_{};
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int spi_fd_ = -1;
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int reset_fd_ = -1;
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int busy_fd_ = -1;
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void spiTransfer(uint8_t *buf, size_t n);
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void wcmd(uint16_t op, const uint8_t *p = nullptr, size_t n = 0);
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void rcmd(uint16_t op, const uint8_t *params, size_t np,
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uint8_t *out, size_t nr);
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uint32_t getIrq(); // NOP-poll: stat1,stat2,irq (no BUSY wait)
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void clearIrq(uint32_t mask);
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uint16_t getErrors(); // returns ErrorStat bits
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bool waitBusy();
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void hardReset();
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bool openGpio(unsigned line, bool out, int &fd_out);
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void setGpioLine(int fd, int val);
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int getGpioLine(int fd);
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bool openSpi(const Config &c);
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// Verbose-mode helpers
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static const char *modeName(uint8_t stat2);
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static const char *cmdName(uint8_t stat1);
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static void imgCalFreqs(uint32_t hz, uint8_t &f1, uint8_t &f2);
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static uint8_t computeLDRO(uint8_t sf, uint8_t bw);
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// Maps target output power to the recommended (PaDutyCycle, PaHpMax) per the
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// LR1121 datasheet PA Settings table. For HP PA: using max drive (duty=4,
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// hp_max=7) at low power draws 22 dBm worth of VBAT current even if SetTxParams
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// limits output — this droops VBAT and triggers LBD. For LP PA: PaHpMax is 0.
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static void computePaConfig(uint8_t pa_sel, int8_t dbm,
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uint8_t &duty, uint8_t &hp_max);
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};
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// ── Implementation ────────────────────────────────────────────────────────────
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inline void Radio::spiTransfer(uint8_t *buf, size_t n)
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{
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spi_ioc_transfer tr{};
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tr.tx_buf = reinterpret_cast<uint64_t>(buf);
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tr.rx_buf = reinterpret_cast<uint64_t>(buf);
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tr.len = static_cast<uint32_t>(n);
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tr.speed_hz = cfg_.spi_hz;
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tr.bits_per_word = 8;
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ioctl(spi_fd_, SPI_IOC_MESSAGE(1), &tr);
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}
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// Write command: opcode [+ params]. Waits for BUSY before and after.
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inline void Radio::wcmd(uint16_t op, const uint8_t *p, size_t n)
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{
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if (!waitBusy()) return;
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uint8_t buf[260];
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buf[0] = op >> 8; buf[1] = op & 0xFF;
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if (p && n) std::memcpy(buf + 2, p, n);
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spiTransfer(buf, 2 + n);
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waitBusy();
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}
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// Read command: opcode [+ params], then clock NOP bytes to retrieve response.
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// Response byte 0 is stat1 (skipped); bytes 1..nr go to out[0..nr-1].
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inline void Radio::rcmd(uint16_t op, const uint8_t *params, size_t np,
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uint8_t *out, size_t nr)
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{
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if (!waitBusy()) return;
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uint8_t cbuf[16]{};
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cbuf[0] = op >> 8; cbuf[1] = op & 0xFF;
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if (params && np) std::memcpy(cbuf + 2, params, np);
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spiTransfer(cbuf, 2 + np);
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if (!waitBusy()) return;
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uint8_t rbuf[260]{};
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spiTransfer(rbuf, nr + 1); // rbuf[0] = stat1 (skip)
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std::memcpy(out, rbuf + 1, nr);
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}
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// Poll current status via 6 NOP bytes (valid at any time, including during TX/RX).
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// Returns irq register [31:0]. MISO: [stat1, stat2, irq31:24, irq23:16, irq15:8, irq7:0].
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inline uint32_t Radio::getIrq()
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{
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uint8_t b[6]{};
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spiTransfer(b, 6);
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return ((uint32_t)b[2] << 24) | ((uint32_t)b[3] << 16)
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| ((uint32_t)b[4] << 8) | (uint32_t)b[5];
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}
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inline void Radio::clearIrq(uint32_t mask)
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{
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uint8_t d[4] = { (uint8_t)(mask >> 24), (uint8_t)(mask >> 16),
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(uint8_t)(mask >> 8), (uint8_t)mask };
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wcmd(OC_CLEAR_IRQ, d, 4);
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}
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inline uint16_t Radio::getErrors()
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{
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uint8_t e[2]{};
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rcmd(OC_GET_ERRORS, nullptr, 0, e, 2);
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return (uint16_t)((e[0] << 8) | e[1]);
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}
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inline bool Radio::waitBusy()
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{
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for (int i = 0; i < 200'000; ++i) {
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if (!getGpioLine(busy_fd_)) return true;
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std::this_thread::sleep_for(std::chrono::microseconds(50));
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}
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if (cfg_.verbose)
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std::fprintf(stderr, "[lr1121] waitBusy: TIMEOUT — chip hung?\n");
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return false;
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}
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inline bool Radio::openGpio(unsigned line, bool out, int &fd_out)
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{
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int chip = ::open(cfg_.gpio_chip, O_RDWR);
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if (chip < 0) {
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if (cfg_.verbose)
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std::fprintf(stderr, "[lr1121] cannot open %s: %m\n", cfg_.gpio_chip);
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return false;
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}
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gpiohandle_request req{};
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req.lineoffsets[0] = line;
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req.lines = 1;
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req.flags = out ? GPIOHANDLE_REQUEST_OUTPUT : GPIOHANDLE_REQUEST_INPUT;
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req.default_values[0] = out ? 1 : 0;
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std::strncpy(req.consumer_label, "lr1121", sizeof(req.consumer_label) - 1);
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int r = ioctl(chip, GPIO_GET_LINEHANDLE_IOCTL, &req);
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::close(chip);
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if (r < 0) {
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if (cfg_.verbose)
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std::fprintf(stderr, "[lr1121] cannot get GPIO line %u: %m\n", line);
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return false;
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}
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fd_out = req.fd;
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return true;
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}
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inline void Radio::setGpioLine(int fd, int val)
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{
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gpiohandle_data d{}; d.values[0] = val;
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ioctl(fd, GPIOHANDLE_SET_LINE_VALUES_IOCTL, &d);
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}
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inline int Radio::getGpioLine(int fd)
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{
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gpiohandle_data d{};
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ioctl(fd, GPIOHANDLE_GET_LINE_VALUES_IOCTL, &d);
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return d.values[0];
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}
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inline void Radio::hardReset()
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{
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setGpioLine(reset_fd_, 0);
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std::this_thread::sleep_for(std::chrono::milliseconds(10));
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setGpioLine(reset_fd_, 1);
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std::this_thread::sleep_for(std::chrono::milliseconds(20));
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}
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inline ChipVersion Radio::getVersion()
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{
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uint8_t v[4]{};
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rcmd(OC_GET_VERSION, nullptr, 0, v, 4);
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return { v[0], v[1], v[2], v[3] };
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}
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inline const char *Radio::modeName(uint8_t stat2)
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{
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switch ((stat2 >> 1) & 0x07) {
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case 0: return "SLEEP";
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case 1: return "STBY_RC";
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case 2: return "STBY_XOSC";
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case 3: return "FS";
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case 4: return "RX";
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case 5: return "TX";
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default: return "?";
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}
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}
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inline const char *Radio::cmdName(uint8_t stat1)
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{
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switch ((stat1 >> 1) & 0x07) {
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case 0: return "CMD_FAIL";
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case 1: return "CMD_PERR";
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case 2: return "CMD_OK";
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case 3: return "CMD_DAT";
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default: return "?";
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}
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}
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inline void Radio::imgCalFreqs(uint32_t hz, uint8_t &f1, uint8_t &f2)
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{
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// Frequency ranges per LR1121 UM Table CalibImage; steps = 4 MHz.
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uint32_t mhz = hz / 1'000'000u;
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uint32_t lo, hi;
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if (mhz < 446) { lo = 430; hi = 440; }
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else if (mhz < 740) { lo = 470; hi = 510; }
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else if (mhz < 890) { lo = 860; hi = 876; }
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else if (mhz < 2000) { lo = 900; hi = 928; }
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else { lo = 2400; hi = 2500; }
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f1 = (uint8_t)(lo / 4);
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f2 = (uint8_t)((hi + 3) / 4);
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}
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inline uint8_t Radio::computeLDRO(uint8_t sf, uint8_t bw)
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{
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// LDRO required when symbol duration > 16 ms.
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static const uint32_t bw_hz[] = { 0, 15625, 31250, 62500, 125000, 250000, 500000 };
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uint32_t bw_val = (bw < 7) ? bw_hz[bw] : 125000;
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return ((1u << sf) * 1000u / bw_val > 16) ? 1 : 0;
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}
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// Maps target dBm to the LR1121 datasheet recommended (PaDutyCycle, PaHpMax).
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//
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// HP PA (pa_sel=0x01, sub-GHz) recommended table from LR1121 datasheet §PA config:
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// ≥22 dBm → duty=4, hp_max=7 ≥20 → 3,5 ≥17 → 2,3
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// ≥14 dBm → duty=2, hp_max=2 ≥10 → 1,1 < 10 → 0,0
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//
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// Using duty=4, hp_max=7 for lower power levels drives all 7 PA stages at full
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// current even though SetTxParams limits the output — VBAT droops under the
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// excess load and triggers LBD, aborting TX before the preamble starts.
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//
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// LP PA (pa_sel=0x00): PaHpMax is always 0; duty controls drive, hp_max unused.
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inline void Radio::computePaConfig(uint8_t pa_sel, int8_t dbm,
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uint8_t &duty, uint8_t &hp_max)
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{
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if (pa_sel == 0x01) { // HP PA
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if (dbm >= 22) { duty = 4; hp_max = 7; }
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else if (dbm >= 20) { duty = 3; hp_max = 5; }
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else if (dbm >= 17) { duty = 2; hp_max = 3; }
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else if (dbm >= 14) { duty = 2; hp_max = 2; }
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else if (dbm >= 10) { duty = 1; hp_max = 1; }
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else { duty = 0; hp_max = 0; }
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} else { // LP PA — PaHpMax not applicable
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hp_max = 0;
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if (dbm >= 14) { duty = 7; }
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else if (dbm >= 10) { duty = 4; }
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else if (dbm >= 0) { duty = 2; }
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else { duty = 0; }
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}
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}
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inline bool Radio::openSpi(const Config &c)
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{
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spi_fd_ = ::open(c.spi_path, O_RDWR);
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if (spi_fd_ < 0) {
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if (c.verbose)
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std::fprintf(stderr, "[lr1121] cannot open %s: %m\n", c.spi_path);
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return false;
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}
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uint8_t mode = SPI_MODE_0, bits = 8;
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ioctl(spi_fd_, SPI_IOC_WR_MODE, &mode);
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ioctl(spi_fd_, SPI_IOC_WR_BITS_PER_WORD, &bits);
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ioctl(spi_fd_, SPI_IOC_WR_MAX_SPEED_HZ, &c.spi_hz);
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return true;
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}
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inline bool Radio::begin(const Config &c)
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{
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cfg_ = c;
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if (!openSpi(c)) return false;
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if (!openGpio(c.reset_gpio, true, reset_fd_)) return false;
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if (!openGpio(c.busy_gpio, false, busy_fd_)) return false;
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{ uint8_t nop = 0x00; spiTransfer(&nop, 1); }
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std::this_thread::sleep_for(std::chrono::milliseconds(1));
|
|
hardReset();
|
|
|
|
ChipVersion ver = getVersion();
|
|
if (c.verbose)
|
|
std::fprintf(stderr, "[lr1121] hw=0x%02X type=0x%02X fw=0x%02X%02X\n",
|
|
ver.hw, ver.type, ver.fw_hi, ver.fw_lo);
|
|
if (ver.type != 0x03) {
|
|
if (c.verbose)
|
|
std::fprintf(stderr, "[lr1121] unexpected type 0x%02X (want 0x03=LR1121)\n",
|
|
ver.type);
|
|
return false;
|
|
}
|
|
if (ver.fw_hi < 0x02 && c.verbose)
|
|
std::fprintf(stderr, "[lr1121] warning: fw=0x%02X%02X — try: sudo ./lora_rx --reset\n",
|
|
ver.fw_hi, ver.fw_lo);
|
|
|
|
if (c.verbose) {
|
|
uint8_t raw = 0;
|
|
rcmd(OC_GET_VBAT, nullptr, 0, &raw, 1);
|
|
// VBAT ≈ raw/34.0 V (from LR1121 formula: raw*5/(4*255)/1.091)
|
|
float vbat = raw / 34.0f;
|
|
std::fprintf(stderr, "[lr1121] VBAT raw=0x%02X (~%.2fV)%s\n", raw, vbat,
|
|
(vbat < 2.5f && raw > 0) ? " ← LOW: check VBAT supply" : "");
|
|
}
|
|
|
|
#define V(msg) do { if (c.verbose) std::fprintf(stderr, "[lr1121] -> " msg "\n"); } while(0)
|
|
|
|
// ── Init sequence (RadioLib config() order, then per-band radio config) ──
|
|
|
|
V("SetStandby(RC)");
|
|
{ const uint8_t a[] = {0x00}; wcmd(OC_SET_STANDBY, a, 1); }
|
|
|
|
// SetFallbackMode before Calibrate — matches RadioLib config() order.
|
|
V("SetFallbackMode(STBY_RC)");
|
|
{ const uint8_t a[] = {0x01}; wcmd(OC_SET_FALLBACK_MODE, a, 1); }
|
|
|
|
V("ClearIrq / SetDioIrqParams(none)");
|
|
clearIrq(IRQ_ALL);
|
|
{ const uint8_t z[8]{}; wcmd(OC_SET_DIOIRQ, z, 8); }
|
|
|
|
V("Calibrate(ALL)");
|
|
{ const uint8_t a[] = {CALIB_ALL}; wcmd(OC_CALIBRATE, a, 1); }
|
|
// Calibrate can take up to several hundred ms. RadioLib does delay(5) + waitBusy.
|
|
std::this_thread::sleep_for(std::chrono::milliseconds(5));
|
|
if (!waitBusy()) {
|
|
if (c.verbose) std::fprintf(stderr, "[lr1121] Calibrate: BUSY stuck\n");
|
|
return false;
|
|
}
|
|
|
|
wcmd(OC_CLEAR_ERRORS);
|
|
{
|
|
uint16_t errs = getErrors();
|
|
if (errs && c.verbose)
|
|
std::fprintf(stderr, "[lr1121] errors after calibrate: 0x%04X%s\n", errs,
|
|
(errs & (1u<<5)) ? " (HF_XOSC_START_ERR — check crystal)" : "");
|
|
}
|
|
|
|
// ── Radio configuration ──────────────────────────────────────────────────
|
|
{ const uint8_t a[] = {c.use_dcdc ? (uint8_t)0x01 : (uint8_t)0x00};
|
|
wcmd(OC_SET_REGMODE, a, 1); }
|
|
|
|
{ const uint8_t a[] = {0x02}; wcmd(OC_SET_PKT_TYPE, a, 1); } // LoRa
|
|
|
|
{ uint32_t f = c.freq_hz;
|
|
const uint8_t a[] = { (uint8_t)(f>>24),(uint8_t)(f>>16),(uint8_t)(f>>8),(uint8_t)f };
|
|
wcmd(OC_SET_RF_FREQ, a, 4); }
|
|
|
|
{ uint8_t f1, f2; imgCalFreqs(c.freq_hz, f1, f2);
|
|
const uint8_t a[] = {f1, f2}; wcmd(OC_CALIBRATE_IMAGE, a, 2);
|
|
if (c.verbose)
|
|
std::fprintf(stderr, "[lr1121] image cal: 0x%02X 0x%02X\n", f1, f2); }
|
|
|
|
{ const uint8_t a[] = {0x00, 0x00}; wcmd(OC_SET_PKT_ADRS, a, 2); }
|
|
|
|
{ uint8_t ldro = computeLDRO(c.sf, c.bw);
|
|
const uint8_t a[] = {c.sf, c.bw, c.cr, ldro};
|
|
wcmd(OC_SET_MOD_PARAM, a, 4);
|
|
if (c.verbose)
|
|
std::fprintf(stderr, "[lr1121] SF=%u BW=0x%02X CR=0x%02X LDRO=%u\n",
|
|
c.sf, c.bw, c.cr, ldro); }
|
|
|
|
{ const uint8_t a[] = {0x00, 0x08, 0x00, 0xFF, 0x01, 0x00};
|
|
wcmd(OC_SET_PKT_PARAM, a, 6); } // preamble=8, explicit hdr, maxlen=255, CRC=on
|
|
|
|
// PA configuration: use the power-matched (duty, hp_max) per the LR1121
|
|
// datasheet. Oversized PA drive (duty=4, hp_max=7) at low power draws
|
|
// excess VBAT current, droops the supply, and fires LBD aborting TX.
|
|
{ uint8_t duty, hp_max;
|
|
computePaConfig(c.pa_sel, c.tx_dbm, duty, hp_max);
|
|
const uint8_t a[] = {c.pa_sel, c.pa_supply, duty, hp_max};
|
|
wcmd(OC_SET_PA_CFG, a, 4);
|
|
if (c.verbose)
|
|
std::fprintf(stderr, "[lr1121] PA: sel=0x%02X supply=0x%02X duty=%u hp_max=%u\n",
|
|
c.pa_sel, c.pa_supply, duty, hp_max); }
|
|
|
|
{ const uint8_t a[] = {(uint8_t)(int8_t)c.tx_dbm, 0x02};
|
|
wcmd(OC_SET_TX_PARAMS, a, 2); }
|
|
|
|
{ const uint8_t a[] = {c.lora_wan ? (uint8_t)0x01 : (uint8_t)0x00};
|
|
wcmd(OC_SET_LORA_NET, a, 1); }
|
|
|
|
// DIO5 = RFSW0, DIO6 = RFSW1 (chip-driven RF switch).
|
|
// standby: both LOW | rx: DIO5=HIGH | tx/tx_hp: DIO6=HIGH
|
|
{ const uint8_t a[] = {0x03, 0x00, 0x01, 0x02, 0x02, 0x00, 0x00, 0x00};
|
|
wcmd(OC_SET_DIO_AS_RFSW, a, 8);
|
|
if (c.verbose) std::fprintf(stderr, "[lr1121] RF switch: DIO5/DIO6\n"); }
|
|
|
|
// Switch to crystal oscillator standby so the crystal is already running
|
|
// when SetTx is issued — avoids cold-start failure on crystal-based modules.
|
|
V("SetStandby(XOSC)");
|
|
{ const uint8_t a[] = {0x01}; wcmd(OC_SET_STANDBY, a, 1); }
|
|
|
|
#undef V
|
|
|
|
if (c.verbose)
|
|
std::fprintf(stderr, "[lr1121] init OK: %u Hz SF%u PA=%s\n",
|
|
c.freq_hz, c.sf, c.pa_sel ? "HP" : "LP");
|
|
return true;
|
|
}
|
|
|
|
inline bool Radio::beginRaw(const Config &c)
|
|
{
|
|
cfg_ = c;
|
|
if (!openSpi(c)) return false;
|
|
if (!openGpio(c.reset_gpio, true, reset_fd_)) return false;
|
|
if (!openGpio(c.busy_gpio, false, busy_fd_)) return false;
|
|
{ uint8_t nop = 0x00; spiTransfer(&nop, 1); }
|
|
std::this_thread::sleep_for(std::chrono::milliseconds(1));
|
|
hardReset();
|
|
return true;
|
|
}
|
|
|
|
inline void Radio::reboot(bool stay_in_bootloader)
|
|
{
|
|
const uint8_t a[] = { (uint8_t)(stay_in_bootloader ? 0x01 : 0x00) };
|
|
wcmd(OC_REBOOT, a, 1);
|
|
std::this_thread::sleep_for(std::chrono::milliseconds(300));
|
|
}
|
|
|
|
inline void Radio::end()
|
|
{
|
|
if (spi_fd_ >= 0) { ::close(spi_fd_); spi_fd_ = -1; }
|
|
if (reset_fd_ >= 0) { ::close(reset_fd_); reset_fd_ = -1; }
|
|
if (busy_fd_ >= 0) { ::close(busy_fd_); busy_fd_ = -1; }
|
|
}
|
|
|
|
inline bool Radio::send(const uint8_t *data, uint8_t n)
|
|
{
|
|
// Crystal must be warm for TX: switch to XOSC standby before SetTx.
|
|
{ const uint8_t a[] = {0x01}; wcmd(OC_SET_STANDBY, a, 1); }
|
|
|
|
wcmd(OC_WRITE_BUF8, data, n);
|
|
{ const uint8_t a[] = {0x00, 0x08, 0x00, n, 0x01, 0x00};
|
|
wcmd(OC_SET_PKT_PARAM, a, 6); }
|
|
|
|
{ const uint8_t a[] = {0x00, 0x00, 0x04, 0x04, 0x00, 0x00, 0x00, 0x00};
|
|
wcmd(OC_SET_DIOIRQ, a, 8); } // DIO9: TX_DONE(bit2) | TIMEOUT(bit10)
|
|
|
|
clearIrq(IRQ_ALL);
|
|
|
|
{ const uint8_t a[] = {0x00, 0x00, 0x00}; wcmd(OC_SET_TX, a, 3); }
|
|
// wcmd() already waited for BUSY low (= PA ramped, preamble on air).
|
|
|
|
if (cfg_.verbose) {
|
|
uint8_t b[6]{}; spiTransfer(b, 6);
|
|
uint32_t irq = ((uint32_t)b[2]<<24)|((uint32_t)b[3]<<16)|((uint32_t)b[4]<<8)|b[5];
|
|
std::fprintf(stderr,
|
|
"[lr1121] after SetTx: mode=%s cmd=%s irq=0x%08X errs=0x%04X\n",
|
|
modeName(b[1]), cmdName(b[0]), irq, getErrors());
|
|
}
|
|
|
|
for (int i = 0; i < 50'000; ++i) {
|
|
uint32_t irq = getIrq();
|
|
if (irq & IRQ_TX_DONE) {
|
|
clearIrq(IRQ_ALL);
|
|
const uint8_t z[8]{}; wcmd(OC_SET_DIOIRQ, z, 8);
|
|
return true;
|
|
}
|
|
std::this_thread::sleep_for(std::chrono::microseconds(100));
|
|
}
|
|
|
|
// Timeout — print diagnostics then clean up.
|
|
if (cfg_.verbose) {
|
|
uint8_t b[6]{}; spiTransfer(b, 6);
|
|
uint32_t irq = ((uint32_t)b[2]<<24)|((uint32_t)b[3]<<16)|((uint32_t)b[4]<<8)|b[5];
|
|
std::fprintf(stderr,
|
|
"[lr1121] TX timeout: mode=%s cmd=%s irq=0x%08X errs=0x%04X\n",
|
|
modeName(b[1]), cmdName(b[0]), irq, getErrors());
|
|
if (irq & (1u<<21))
|
|
std::fprintf(stderr,
|
|
"[lr1121] ↳ LBD (Low Battery Detect): VBAT drooped under PA load.\n"
|
|
"[lr1121] Check VBAT supply / decoupling. Try lower tx_dbm or pa_sel=LP.\n");
|
|
}
|
|
|
|
clearIrq(IRQ_ALL);
|
|
const uint8_t z[8]{}; wcmd(OC_SET_DIOIRQ, z, 8);
|
|
{ const uint8_t a[] = {0x01}; wcmd(OC_SET_STANDBY, a, 1); }
|
|
return false;
|
|
}
|
|
|
|
inline int Radio::receive(uint8_t *buf, uint8_t cap, uint32_t timeout_ms,
|
|
RxInfo *rx_info)
|
|
{
|
|
{ const uint8_t a[] = {0x01}; wcmd(OC_SET_STANDBY, a, 1); } // XOSC warm
|
|
|
|
{ const uint8_t a[] = {0x00, 0x00, 0x04, 0x88, 0x00, 0x00, 0x00, 0x00};
|
|
wcmd(OC_SET_DIOIRQ, a, 8); } // RX_DONE(bit3)|CRC_ERR(bit7)|TIMEOUT(bit10)
|
|
|
|
clearIrq(IRQ_ALL);
|
|
|
|
uint32_t t = (timeout_ms == 0) ? 0x00FF'FFFFu
|
|
: (uint32_t)(timeout_ms * 32768ull / 1000);
|
|
{ const uint8_t a[] = {(uint8_t)(t>>16),(uint8_t)(t>>8),(uint8_t)t};
|
|
wcmd(OC_SET_RX, a, 3); }
|
|
|
|
for (;;) {
|
|
uint32_t irq = getIrq();
|
|
|
|
if (irq & IRQ_RX_DONE) {
|
|
if (rx_info) {
|
|
uint8_t ps[3]{};
|
|
rcmd(OC_GET_PKT_STATUS, nullptr, 0, ps, 3);
|
|
rx_info->rssi_dbm = (int8_t)(-(int)ps[0] / 2);
|
|
rx_info->snr_db = (int8_t)((int8_t)ps[1] / 4);
|
|
rx_info->signal_rssi_dbm = (int8_t)(-(int)ps[2] / 2);
|
|
}
|
|
if (irq & IRQ_CRC_ERR) { clearIrq(IRQ_ALL); return -2; }
|
|
|
|
uint8_t stat[2]{};
|
|
rcmd(OC_GET_RXBUF_STA, nullptr, 0, stat, 2);
|
|
uint8_t len = (stat[0] < cap) ? stat[0] : cap;
|
|
uint8_t p[2] = { stat[1], len };
|
|
rcmd(OC_READ_BUF8, p, 2, buf, len);
|
|
wcmd(OC_CLEAR_RXBUF);
|
|
clearIrq(IRQ_ALL);
|
|
return (int)len;
|
|
}
|
|
|
|
if (irq & IRQ_TIMEOUT) { clearIrq(IRQ_ALL); return -1; }
|
|
std::this_thread::sleep_for(std::chrono::milliseconds(1));
|
|
}
|
|
}
|
|
|
|
} // namespace lr1121
|